Post Layout Watermarking Design Method for IP Protection

The progress of semiconductor manufacture process technology has made it possible to mount a huge number of transistors on a chip that includes a perfect system on it. Nevertheless, while the design reuse is effective in reducing both the SOC design cost and TAT (Turn Around time) of development, the design method also exposes the risk on security. IP (Intellectual Property) reuse plays an important role in modern IC design. As most IP designs need a great deal of time and efforts for development or verification, the IP owners desire some guarantees that those contents are not illegally re-distributed by the consumer. IP users also desire some guarantee that the contents they bought are legal. Therefore IPP (IP Protection) technique is get concerned inevitably. In recent years, watermarking technology has become an effective fashion for IPP, both in pre-processing and post-processing. Most of the techniques converge on the pre-processing that the watermark-constrained IC design is designed form the top stage so that it leads to extra design costs such as wire-length, interconnection delay, etc. There are several watermarking techniques on post-processing which try to add watermark constraints into the designed IC without damaging the origin. But the extra cost brought by the watermarking is really a trouble to the designers. In this thesis, the author introduced a new watermarking system for IPP on post-layout design stage. The author conducted the watermarking system in such process: First, the signature of the designer is encrypted with a secret key by DES (Data Encryption Standard) to produce a bit string. Second, the bit string is then embedded into the layout design as constraints by using a specific incremental router. Third, the signature can be extracted accurately from the watermarked design by the system. The proposed IPP system has a strong resistance to the attack on watermarking due to the DES functionality. This watermarking technique uniquely identifies the circuit origin, yet is difficult to be detected or fabricated without the IPP system. We evaluated the watermarking system on IBM-PLACE 2.0 benchmark suites. The experimental results show the system robustness and strength: the system success probability achieves 100% in suitable time with no extra area and wire length cost on design performances. CONTENTS 4 _________________________________________________________________________________